FMCJESDADC1 hdl reference design for A10SOC carrier

FMCJESDADC1 hdl reference design for ZCU102 carrier

FMCOMMS7 hdl reference design

USDRX1 ulstrasound hdl reference design

Paul's attempt to add scatter-gather support for ADI AXI_DMAC IP

hdl_2019_r1 release tag

Tag for the hdl_2018_r2 release

Solves the following EZ questions:
https://ez.analog.com/linux-device-drivers/linux-software-drivers/f/q-a/108820/ad9208-on-zcu102-linux-problems
https://ez.analog.com/fpga/f/q-a/102373/ad9208-reference-clock-from-board-sma-j3-issue

fmcomms2 port to a10soc

DAQ2 port to iWave FPGA development platform.

A FIR filter integration example for FMCOMMS2.